GUJCOST Minor Research Project: “New Design Level Testing Methods for Performance Improvement of VLSI in Nanometer Region”

To reduce the size of test data, to improve the quality of testing and also to optimize test time and test power, new functional fault model has to be defined for describing physical defects in integrated circuits with nm technology. For this new approach, the automatic test pattern generation (ATPG) methods and external testing methods involving ATEs need to be redesigned. This project involves the redesigning the current ATPG for shrinking technology.