This project focuses on the study and simulation of the low noise and low power CMOS circuit design techniques. In the modern era, with the evident of the new design technologies and sophisticated design methods available, the VLSI technology has witnessed a tremendous growth. With the growth in VLSI design the number of transistor on a single chip have gone very high drastically. With increased density of the chip the power requirement of the chip also goes high. The major challenge is to design the circuit such that the power requirement decreases even in the extremely high density chip. To reduce the power requirement of the chip it is necessary to scale it down. Scaling the device will introduce new problems like Hot carrier effect, Sub threshold conduction, VTC shift etc. The main aim of the project is to analyze the problem associated with the scaling of the device. After the thorough understanding the problems the effort is to make the device such that it can withstand all the previous properties with as low power and low noise as possible. The work includes the detailed study of scaling of the device, voltage and power requirement of the device. It also includes the simulation of the device with high end VLSI tools available in the market like Mentor graphics or Cadence. The parasitic associated with the device will also be calculated. Thus the project provide the detailed study of low power low noise CMOS design with an added feature of Automatic Gain Control for amplifier that can be used in biomedical applications.