This thesis is about the design of a Ka-band Low Noise Amplifier(LNA) operating betwee frequency ranges of 26.5-30 GHz. The technical specification of any LNA includes a gain, which is approximately between 15-20 dB and minimum low noise figure < 3 dB. The transistor used to design is a p-HEMT model manufactured by United Monolithic Semiconductor which is a low noise transistor model. The thesis commits the results of the design LNA as for overall frequency range i.e.26.5-30 Ghz. It also satisfies the use of Cascode transistor which assists in providing a gain between 16-14dB and a minimum Noise Figure(NFmin) of 2.12-2.13 dB and Noise Figure(NF) < 3 dB. The essential benefit of using Cascode topology is to get high gain and further more application of resistor on drain side provides necessary stability to the design. The matching networks attached at input and output ports helped in achieving gain stability at the respective ports.
As more than two billions of transistors are integrated on same die with clock frequencies well above several gigahertz. Because of this, device noise has become the primarily concern for digital ICs relatively which is traditionally considered to be relatively immune from the noise. So, at high frequency, noise is not negligible for digital ICs. Specifically, switching noise i.e power/ground noise has become a primary design criterion for both mixed-signal and high performance synchronous digital ICs. Therefore, power integrity has become the major issue which should be addressed at the system level considering the parasitic effect on package and board. Generally, from a system perseptive, Power Integrity was not considered by the circuit, package and board designers, but if chip does not meet the PI and EMC requirement then the circuit has to be re-designed with a dramatic increase in terms of NRE costs, and subsequent delay in the product chain, thus missing critical time-to-market windows. So, with the customer’s requirement and an increasingly aggressive competition in the market leads to deploy an effective and reusable solutions for a wide range of applications, an accurate and practical modelling approach for the system PDN to estimate the power integrity and EMC behavior before fabrication, and the development of an overall PI/EMC-aware design methodology. In this work, a die, package and board modeling and co-simulation methodology is presented which can be seamlessly integrated into the standard design flow. So, system is breakdown into the multiple components and system level modelling is done for each components to observe the individual performance of this components. Then system level response can be seen by combining them together. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins. As setup is done manually by user in EDA tools which takes sufficient amount of time. So, to reduce the setup time, tools are automated for performing certain task. PI/EMC-aware design methodology.repeater cell's count.
FMCW, FMICW and Pulse wave RF signals based Radar altimeters are used for measurement of correct distance between the ground or the object below it in all weather condition. The Antenna and Radome Assembly, RF Transceiver Module, DSP Module alongwith Power Supply Card are the main sub-systems of Radar Altitude Sensor. The transmitted signal has to be correctly and instantly extracted by the system from the received signal; hence, it is mandatory to build a system with high SNR. To achieve good results, accurate hardware selection and interfacing it with the FPGA is also an important task. Then after, the Analog signal is converted into a digital form and a Filter has to be selected according to the output of DDS signal. The proposed project is to develop and design a well interfaced system according to the requirements of the altimeter. The assigned project work involves selection of appropriate DDS and interfacing it with the FPGA(here : Virtex-6 Zync) to be used for Radar Altimeter. For nalizing the interfacing scheme, detail study of whole system as well as systems component is done during the project. Following the finalization of interfacing components, a VHDL code has been developed to interface and configure various peripheral components with Virtex-6 and Zync FPGA. The functionality of components has been tested and validated for intended application.